Vhdl Assignment

These physical components are operating simultaneously. The moment they are powered, they will “concurrently” fulfill their functionality.Note that while, in practice, the AND gate has a delay to produce a valid output, this does not mean that the OR gate will stop its functionality and wait until the output of the AND gate is produced.Furthermore, using the sequential VHDL, we can easily describe a digital circuit in a behavioral manner.

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If we consider the operation of the three logic gates of this figure, we observe that each gate processes its current input(s) in an independent manner from other gates.

This figure illustrates a conditional signal assignment with three “when” clauses.

Let’s review the main features of the selected signal assignment and the conditional signal assignment.

After giving some examples, we will briefly compare these two types of signal assignment statements.

Please see my article introducing the concept of VHDL if you're not familiar with it.


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